View LT1941-15_8256421.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

lt1941 1 1941fb typical application description triple monolithic switching regulator the lt ? 1941 is a triple current mode dc/dc converter with internal power switches. two of the regulators are step-down converters with 3a and 2a power switches. the third regulator can be con? gured as a boost, inverter or sepic converter and has a 1.5a power switch. all three converters are synchronized to a 1.1mhz oscillator. the two step-down converters run with opposite phase, reducing input ripple current. the output voltages are set with external resistor dividers and each regulator has independent shutdown and soft-start circuits. each regulator generates a power good signal when its output is in regulation, easing power supply sequencing and interfacing with microcontrollers and dsps. the high switching frequency offers several advantages by permitting the use of small inductors and ceramic capacitors, leading to a very small triple output solution. the constant switching frequency, combined with low impedance ceramic capacitors, result in low, predictable output ripple. with its wide input voltage range of 3.5v to 25v, the lt1941 regulates a broad array of power sources from 4-cell batteries and 5v logic rails to unregulated wall transformers, lead acid batteries and distributed-power supplies. l , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. features applications n wide input range: 3.5v to 25v n three switching regulators with internal power switches: 3a step-down, 2a step-down, 1.5a inverting/boost n antiphase switching reduces ripple n independent shutdown/soft-start pins n independent power good indicators ease supply sequencing n input voltage power good indicators monitor input supply n uses small inductors and ceramic capacitors n constant 1.1mhz switching frequency n thermally enhanced 28-lead tssop package n cable modems n dsl modems n distributed power regulation n wall transformer regulation n disk drives n dsp power figure 1. triple output power supply: 3.3v, 1.8v, C12v start-up waveforms with sequencing v out2 v out1 lt1941 v in gnd 0.22f 22f 1000pf 1.5nf 1.5nf 3300pf 13.7k 133k 2.49k 10k v in 4.7v to 14v 5good 12good v out1 1.8v 2.4a v out3 C12v 350ma* 3.3h 3h 22h 22h 10.7k 13.7k 7.32k 3.3k 1.5k 1941 f01 130k 100k 100k 100k 100k pgood1 pgood2 pgood3 v out2 3.3v 1.4a 0.22f 33f 1f 10f *240ma at v in = 5v, 550ma at v in = 12v 10f 22nf pgood1 pgood2 pgood3 boost2 sw2 fb2 v c2 sw1 fb1 v c1 runss2 bias1 bias2 v c3 runss3 runss1 sw3 nfb fb3 5good 12good boost1 1.5nf run/ss 2v/div 2ms/div v out1 2v/div v out2 5v/div v out3 10v/div i vin(ave) 1a/div pgood2 5v/div 1941 f01b
lt1941 2 1941fb the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in , v bias1 , v bias2 = 5v, v boost1 , v boost2 = 8v, unless otherwise noted. (note 2) pin configuration absolute maximum ratings v in pin ........................................................(C0.3v), 25v boost pin voltage ...................................................35v boost above sw pin ...............................................25v bias1, bias2 pins ....................................................25v pgood, 5good, 12good pins .................................25v run/ss, v c , fb, nfb pins ..........................................3v sw1, sw2 voltage .....................................................v in sw3 voltage .............................................................40v maximum junction temperature (note 6) ............ 125c operating ambient temperature range (note 2) ....................................................C40c to 85c storage temperature range .................. C65c to 150c lead temperature (soldering, 10 sec)................... 300c (note 1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view fe package 28-lead plastic tssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v in v in sw1 sw1 boost1 pgood1 v c1 fb1 pgood2 v c2 fb2 run/ss1 run/ss2 run/ss3 bias2 sw3 pgnd v in boost2 sw2 v in pgood3 fb3 nfb v c3 5good 12good bias1 29 t jmax = 125c, ja = 25c/w exposed pad (pin 29) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking package description temperature range lt1941efe#pbf lt1941efe#trpbf lt1941efe 28-lead plastic tssop C40c to 85c lead based finish tape and reel part marking package description temperature range lt1941efe lt1941efe#tr lt1941efe 28-lead plastic tssop C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ electrical characteristics parameter conditions min typ max units minimum operating voltage l 3.3 3.5 v v in quiescent current not switching 2 3.5 ma bias1 quiescent current not switching 5 7.5 ma bias2 quiescent current not switching 1.6 2.2 ma shutdown current v runss1,2,3 = 0v 50 75 a reference voltage line regulation 5v < v in < 25v 0.01 %/v v c source current v c = 0.6v 100 a v c sink current v c = 0.6v 100 a v c clamp voltage 1.7 v switching frequency l 0.9 1.1 1.35 mhz
lt1941 3 1941fb the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in , v bias1 , v bias2 = 5v, v boost1 , v boost2 = 8v, unless otherwise noted. (note 2) electrical characteristics parameter conditions min typ max units switching phase sw1 to sw2 sw1 to sw3 150 C30 180 0 210 30 deg deg foldback frequency v fb = 0v 200 khz run/ss current 123 a run/ss threshold 0.4 0.6 v 5good threshold v in rising 4.5 v 5good voltage output low i 5good = 125a, v in = 4v 0.2 0.4 v 5good leakage v 5good = 2v 10 400 na 12good threshold v in rising 10.8 v 12good voltage output low i 12good = 125a 0.2 0.4 v 12good leakage v 12good = 2v, v in = 12v 10 400 na pgood voltage output low i pgood = 200a 0.2 0.4 v pgood pin leakage v pgood = 2v 10 400 na 3a step-down fb1 voltage l 618 613 628 638 638 mv mv fb1 pin bias current l 50 500 na pgood1 threshold offset v fb rising 54 mv frequency shift threshold on fb1 0.35 v error ampli? er transconductance 1700 mhos error ampli? er voltage gain 500 v/v v c switching threshold 0.9 v v c1 to switch current gain 5a/v switch 1 current limit (note 3) v in = 12v, v boost1 , v boost2 = 15v l 3 4.3 6 a switch 1 v cesat (note 7) i sw = 2.5a 400 600 mv boost1 pin current i sw = 2.5a 40 60 ma switch 1 leakage current 0.01 10 a minimum boost voltage above switch (note 4) 1.8 2.5 v maximum duty cycle l 78 88 % 2a step-down fb2 voltage l 618 613 628 638 638 mv mv fb2 pin bias current l 50 500 na pgood2 threshold offset v fb rising 54 mv frequency shift threshold on fb2 0.35 v error ampli? er transconductance 1700 mhos error ampli? er voltage gain 500 v/v v c switching threshold 0.9 v v c2 to switch current gain 3.6 a/v switch 2 current limit (note 3) v in = 12v, v boost1 , v boost2 = 15v l 2 2.9 4.1 a switch 2 v cesat (note 7) i sw = 1.5a 450 600 mv boost2 pin current i sw = 1.5a 26 40 ma
lt1941 4 1941fb the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in , v bias1 , v bias2 = 5v, v boost1 , v boost2 = 8v, unless otherwise noted. (note 2) electrical characteristics parameter conditions min typ max units switch 2 leakage current 0.01 10 a minimum boost voltage above switch (note 4) 1.8 2.5 v maximum duty cycle l 78 88 % 1.5a inverting/boost fb3 voltage l 1.23 1.22 1.25 1.27 1.27 v v fb3 pin bias current l 800 1400 na nfb voltage l C15 0 15 mv nfb pin bias current l 60 500 na nfb3 voltage (v fb3 -v nfb ) l 1.212 1.205 1.24 1.258 1.260 v v fb3 pin output current v fb3 = 1.35v, v nfb = C0.1v l 150 350 a pgood3 threshold offset v fb rising 120 mv error ampli? er transconductance 800 mhos error ampli? er voltage gain 150 v/v v c switching threshold 1.1 v v c3 to switch current gain 5a/v frequency shift threshold on fb3 0.65 v switch 3 current limit (note 5) l 1.5 2 2.9 a switch 3 v cesat i sw = 1a 240 320 mv bias2 pin current i sw = 1a 30 45 ma switch 3 leakage current 0.01 10 a maximum duty cycle l 77 86 % note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt1941e is guaranteed to meet performance speci? cations from 0c to 70c. speci? cations over the C40c to 85c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 3: current limit is guaranteed by design and/or correlation to static test. slope compensation reduces current limit at higher duty cycles. note 4: this is the minimum voltage across the boost capacitor needed to guarantee full saturation of the internal power switch. note 5: current limit is guaranteed by design and/or correlation to static test. note 6: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the speci? ed maximum operating junction temperature may impair device reliability. note 7: guaranteed by design, not 100% tested.
lt1941 5 1941fb typical performance characteristics sw1 current limit vs duty cycle sw2 current limit vs duty cycle boost2 pin current sw1 v cesat sw2 v cesat sw3 v cesat ef? ciency, v out1 = 1.8v ef? ciency, v out2 = 3.3v ef? ciency, v out3 = C12v load current (a) 0 efficiency (%) 70 80 2 1941 g01 60 50 0.5 1 1.5 2.5 90 v in = 5v t a = 25c load current (a) 0 50 efficiency (%) 60 70 80 90 0.25 0.5 0.75 1 1941 g07 1.25 1.5 v in = 5v t a = 25c load current (ma) 0 50 efficiency (%) 60 70 80 90 50 100 150 200 1941 g08 250 300 v in = 5v t a = 25c switch current (a) 0 0 switch voltage (mv) 100 200 300 400 500 0.5 1 1.5 2 1941 g02 2.5 3 t a = 25c duty cycle (%) 0 current limit (a) 3.0 4.0 5.0 80 1941 g03 2.0 1.0 2.5 3.5 4.5 1.5 0.5 0 20 40 60 100 typical minimum duty cycle (%) 0 0 current limit (a) 0.5 1.0 1.5 2.0 2.5 3.0 20 40 60 80 1941 g06 100 typical minimum switch current (a) 0 0 switch voltage (mv) 100 200 300 400 600 500 0.5 1 1941 g09 1.5 2 t a = 25c sw2 pin current (a) 0 boost current (ma) 20 30 2 1941 g11 10 0 0.5 1 1.5 40 t a = 25c switch current (a) 0 switch voltage (mv) 100 200 300 400 500 1941 g10 0 0.25 0.5 0.75 1 1.25 1.5 t a = 25c
lt1941 6 1941fb typical performance characteristics run/ss thresholds vs temperature minimum input voltage v out2 = 5v minimum input voltage v out2 = 3.3v frequency vs temperature switching frequency vs % of feedback voltage i run/ss vs temperature temperature (c) C50 frequency (mhz) 1.3 1.2 1.1 1.0 0.9 C25 0 25 50 1941 g13 75 100 125 % of feedback voltage 0 0 switching frequency (mhz) 0.2 0.4 0.6 0.8 1.0 1.2 20 40 60 80 1941 g14 100 t a = 25c temperature (c) C50 0 run/ss current (a) 0.5 1.0 1.5 2.0 3.0 C25 02550 1941 g15 75 100 125 2.5 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 run/ss thresholds (v) temperature (c) C50 25 75 1941 g16 C25 0 50 100 125 to switch to run load current (ma) 1 5.0 minimum input voltage (v) 7.0 7.5 8.0 10 100 1000 1941 g17 6.5 6.0 5.5 v in to start d boost = cmdsh-3 t a = 25c v in to run boost diode tied to output boost diode tied to input load current (ma) 1 3.0 minimum input voltage (v) 5.0 5.5 6.0 10 100 1000 1941 g18 4.5 4.0 3.5 v in to start v in to run boost diode tied to output boost diode tied to input d boost = cmdsh-3 t a = 25c boost1 pin current v fb3 vs temperature v fb1 , v fb2 vs temperature sw1 pin current (a) 0 0 boost current (ma) 10 20 30 40 50 0.5 1 1.5 2 1941 g04 2.5 3 t a = 25c temperature (c) C50 1.220 v fb (v) 1.235 1.250 1.265 1.280 C25 0 25 50 1941 g05 75 100 125 temperature (c) C50 0.605 v fb (v) 0.615 0.625 0.635 0.645 C25 0 25 50 1941 g12 75 100 125
lt1941 7 1941fb pin functions v in (pins 1, 2, 22, 25): the v in pins supply current to the lt1941s internal circuitry and to the internal power switches. these pins must be tied to the same source and locally bypassed. sw1, sw2, sw3 (pins 3, 4, 23, 27): the sw pins are the outputs of the internal power switches. connect these pins to the inductors and switching diodes. boost1, boost2 (pins 5, 24): the boost pins are used to provide drive voltages, higher than the input voltage, to the internal bipolar npn power switches. tie through a diode from v out or from v in . pgood1, pgood2, pgood3 (pins 6, 9, 21): the pgood pins are the open-collector outputs of an internal compara- tor. pgood remains low until the fb pin is within 10% of the ? nal regulation voltage. as well as indicating output regulation, the pgood pins can sequence the switching regulators. leave these pins unconnected if unused. the pgood outputs are valid when v in is greater than 3.5v and any of the run/ss pins are high. they are not valid when all run/ss pins are low. v c1 , v c2 , v c3 (pins 7, 10, 18): the v c pins are the outputs of the internal error amps. the voltages on these pins control the peak switch currents. these pins are normally used to compensate the control loops. each switching regulator can be shut down by pulling its respective v c pin to ground with an nmos or npn transistor. fb1, fb2, fb3 (pins 8, 11, 20): the lt1941 regulates each feedback pin to either 0.628v (fb1, fb2) or 1.25v (fb3). connect the feedback resistor divider taps to these pins. run/ss1, run/ss2, run/ss3 (pins 12, 13, 14): the run/ss pins are used to shut down the individual switching regulators and the internal bias circuits. they also provide a soft-start function. to shut down either regulator, pull the run/ss pin to ground with an open drain or collec- tor. tie a capacitor from this pin to ground to limit switch current during start-up. if neither feature is used, leave these pins unconnected. bias1 (pin 15): the bias1 pin supplies the current to the lt1941s internal regulator. tie this pin to the lowest available voltage source above 2.35v (either v in , v out or any other available supply). 12good (pin 16): the 12good pin is the open-collector output of an internal comparator. 12good remains low until v in is within 10% of 12v. the pin pulls low when the part is in shutdown. leave this pin unconnected if unused. 5good (pin 17): the 5good pin is the open-collector output of an internal comparator. 5good remains low until v in is within 10% of 5v. the pin pulls low when the part is in shutdown. leave this pin unconnected if unused. nfb (pin 19): the lt1941 contains an op amp con? gured with an output at fb3, noninverting terminal at gnd and an inverting terminal at nfb. connect the feedback resistor network virtual ground at this node if regulating negative voltages. otherwise, tie this node to fb3. pgnd (pin 26): tie directly to local ground plane. bias2 (pin 28): the bias2 pin supplies the current to the driver of sw3. tie this pin to the lowest available voltage source above 2.5v (either v in , v out or any other available supply). exposed pad (pin 29): ground. the underside exposed pad metal of the package provides both electrical contact to ground and good thermal contact to the printed circuit board. the exposed pad must be soldered to the circuit board ground for proper operation.
lt1941 8 1941fb block diagram the lt1941 is a constant frequency, current mode, triple output regulator with internal power switches. the three regulators share common circuitry including input source, voltage reference and oscillator, but are otherwise inde- pendent. operation can be best understood by referring to the block diagram. if the run/ss pins are tied to ground, the lt1941 is shut down and draws 50a from the input source tied to v in . internal 2a current sources charge external soft-start capacitors, generating voltage ramps at these pins. if any of the run/ss pins exceed 0.6v, the internal bias circuits turn on, including the internal regulator, reference and 1.1mhz master oscillator. each switching regulator will only begin to operate when its corresponding run/ss pin reaches 1v. the master oscillator generates three clock signals, with the two signals for the step-down regulators out of phase by 180. the three switchers are current mode regulators. instead of directly modulating the duty cycle of the power switch, the feedback loop controls the peak current in the switch during each cycle. compared to voltage mode control, cur- rent mode control improves loop dynamics and provides cycle-by-cycle current limit. the block diagram shows only one of the two step-down switching regulators. a pulse from the slave oscillator sets the rs ? ip-? op and turns on the internal npn bipo- lar power switch. current in the switch and the external inductor begins to increase. when this current exceeds a level determined by the voltage at v c , current comparator c1 resets the ? ip-? op, turning off the switch. the current in the inductor ? ows through the external schottky diode and begins to decrease. the cycle begins again at the next pulse from the oscillator. in this way, the voltage on the v c pin controls the current through the inductor to the output. the internal error ampli? er regulates the output voltage by continually adjusting the v c pin voltage. the threshold for switching on the v c pin is 1v and an active clamp of 1.7v limits the output current. the run/ss pin voltage also clamps the v c pin voltage. as the internal current source charges the external soft-start capacitor, the current limit increases slowly. an internal op amp allows the part to regulate negative voltages using only two external resistors. each switcher contains an extra, independent oscillator to perform frequency foldback during overload conditions. this slave oscillator is normally synchronized to the master oscillator. a comparator senses when v fb is less than 50% of its regulated value and switches the regulator from the master oscillator to a slower slave oscillator. the v fb pin is less than 50% of its regulated value during start-up, short circuit and overload conditions. frequency foldback helps limit switch current under these conditions. the switch drivers for sw1 and sw2 operate either from v in or from the boost pin. an external capacitor and diode are used to generate a voltage at the boost pin that is higher than the input supply. this allows the driver to saturate the internal bipolar npn power switch for ef? cient operation. the bias1 pin allows the internal circuitry to draw its current from a lower voltage supply than the input, also reducing power dissipation and increasing ef? ciency. if the voltage on the bias1 pin falls below 2.35v, then its quiescent current will ? ow from v in . the bias2 pin allows the driver for sw3 to draw its current from a lower voltage supply than the input. this reduces power dissipation within the part and increases ef? ciency. if the voltage on the bias2 pin falls below 2v , then sw3 will lock out and will not be able to turn on until bias2 rises above 2.1v . a power good comparator trips when the fb pin is at 91% of its regulated value. the pgood output is an open-collector transistor that is off when the output is in regulation, allowing an external resistor to pull the pgood pin high. power good is valid when the lt1941 is enabled and v in > 3.5v. input power good comparators monitor the input supply. the 5good and 12good pins are open-collector outputs of internal comparators. the 5good pin remains low until the input is within 10% of 5v. the 12good pin remains low until the input is within 10% of 12v. the 5good and 12good pins are valid as long as v in is greater than 1.1v. both the 5good and 12good pins will sink current when the part is in shutdown, independent of the voltage at v in.
lt1941 9 1941fb block diagram inverting/boost switching regulator one of two step-down switching regulators figure 2. block diagram of the lt1941 with associated external components C + C + C + C + C + r sq slave osc int reg and ref master osc run/ss1 run/ss2 2a bias1 2a clk1 clk2 clk3 v in 0.628v 54mv i limit clamp 1.7v run/ss pgood c c c f r c gnd error amp slope v c 0.9v 0.35v clk r1 c1 c in sw fb boost v in v in d2 c3 l1 d1 c1 r2 out 1941 f02 run/ss3 2a C + 4.5v 5good v in C + C + 10.8v 12good 1.25v run/ss 0.4v nfb fb3 0.6v 1.12v C + C + C + error amp c2 C + C + C + v c3 r clk3 q s bias2 sw3 v in sw3 l3 c4 v out3 d3 boost pgnd q1 driver 0.01 ramp generator slave oscillator pgood3 v in sw3 l4a l4b d4 c6 Cv out3 c5 inverting 3 C + for positive outputs for negative outputs v out3 r3 (external) fb3 nfb r4 (external) fb3 Cv out3 r3 (external) nfb r4 (external)
lt1941 10 1941fb applications information step-down considerations fb resistor network the output voltage is programmed with a resistor divider (refer to the block diagram) between the output and the fb pin. choose the resistors according to r1 = r2(v out /628mv C 1) r2 should be 10k or less to avoid bias current errors. input voltage range the minimum operating voltage is determined either by the lt1941s undervoltage lockout of ~3.3v or by its maximum duty cycle. the duty cycle is the fraction of time that the internal switch is on and is determined by the input and output voltages: dc = (v out + v f )/(v in C v sw + v f ) where v f is the forward voltage drop of the catch diode (~0.4v) and v sw is the voltage drop of the internal switch (~0.3v at maximum load). this leads to a minimum input voltage of: v in(min) = (v out + v f )/dc max C v f + v sw with dc max = 0.78. the maximum operating voltage is determined by the absolute maximum ratings of the v in and boost pins and by the minimum duty cycle dc min = 0.15: v in(max) = (v out + v f )/dc min C v f + v sw this limits the maximum input voltage to ~14v with v out = 1.8v and ~19v with v out = 2.5. note that this is a restriction on the operating input voltage; the circuit will tolerate input voltage transients up to the absolute maximum rating. inductor selection and maximum output current a good ? rst choice for the inductor value is l = (v out + v f )/1.6 for sw1 l = (v out + v f )/1.1 for sw2 where v f is the voltage drop of the catch diode (~0.4v) and l is in h. with this value the maximum load current will be 2.1a for sw1 and 1.4a for sw2, independent of input voltage. the inductors rms current rating must be greater than the maximum load current and its saturation current should be at least 30% higher. for highest ef? ciency, the series resistance (dcr) should be less than 0.1. table 1 lists several vendors and types that are suitable. table 1. inductors part number value (h) i sat (a) dcr () height (mm) sumida cr43-1r4 1.4 2.52 0.056 3.5 cr43-2r2 2.2 1.75 0.071 3.5 cdrh3d16-1r5 1.5 1.55 0.040 1.8 cdrh4d28-3r3 3.3 1.57 0.049 3.0 cdrh4d18-1r0 1.0 1.70 0.035 2.0 cdc5d23-2r2 2.2 2.50 0.03 2.5 cdrh5d28-2r6 2.6 2.60 0.013 3.0 coilcraft do1606t-152 1.5 2.10 0.060 2.0 do1606t-222 2.2 1.70 0.070 2.0 do1608c-152 1.5 2.60 0.050 2.9 do1608c-222 2.2 2.30 0.070 2.9 do1608c-332 3.3 2.00 0.080 2.9 do1608c-472 4.7 1.50 0.090 2.9 mos6020-222 2.2 2.15 0.035 2.0 mos6020-332 3.3 1.8 0.046 2.0 mos6020-472 4.7 1.5 0.050 2.0 do3314-222 2.2 1.6 0.200 1.4 toko (d62f)847fy-2r4m 2.4 2.5 0.037 2.7 (d73lf)817fy-2r2m 2.2 2.7 0.03 3.0 the optimum inductor for a given application may differ from the one indicated by this simple design guide. a larger value inductor provides a slightly higher maximum load current and will reduce the output voltage ripple. if
lt1941 11 1941fb applications information your load is lower than the maximum load current, then you can relax the value of the inductor and operate with higher ripple current. this allows you to use a physically smaller inductor or one with a lower dcr resulting in higher ef? ciency. be aware that if the inductance differs from the simple rule above, then the maximum load current will depend on input voltage. in addition, low inductance may result in discontinuous mode operation, which further reduces maximum load current. for details of maximum output current and discontinuous mode operation, see linear technologys application note an44. finally, for duty cycles greater than 50% (v out /v in > 0.5), a minimum inductance is required to avoid subharmonic oscillations. see an19. the current in the inductor is a triangle wave with an average value equal to the load current. the peak switch current is equal to the output current plus half the peak-to-peak inductor ripple current. the lt1941 limits its switch cur- rent in order to protect itself and the system from overload faults. therefore, the maximum output current that the lt1941 will deliver depends on the switch current limit, the inductor value and the input and output voltages. when the switch is off, the potential across the inductor is the output voltage plus the catch diode drop. this gives the peak-to-peak ripple current in the inductor: i l = (1 C dc)(v out + v f )/(l ? f) where f is the switching frequency of the lt1941 and l is the value of the inductor. the peak inductor and switch current is: i swpk = i lpk = i out + i l /2 to maintain output regulation, this peak current must be less than the lt1941s switch current limit i lim . for sw1, i lim is at least 3a at low duty cycles and decreases linearly to 2.4a at dc = 0.8. for sw2, i lim is at least 2a for at low duty cycles and decreases linearly to 1.6a at dc = 0.8. the maximum output current is a function of the chosen inductor value: i out(max) = i lim C i l /2 = 3 ? (1 C 0.25 ? dc) C i l /2 for sw1 = 2 ? (1 C 0.25 ? dc) C i l /2 for sw2 choosing an inductor value so that the ripple current is small will allow a maximum output current near the switch current limit. one approach to choosing the inductor is to start with the simple rule given above, look at the available inductors and choose one to meet cost or space goals. then use these equations to check that the lt1941 will be able to deliver the required output current. note again that these equations assume that the inductor current is continu- ous. discontinuous operation occurs when i out is less than i l /2. output capacitor selection for 5v and 3.3v outputs, a 10f, 6.3v ceramic capacitor (x5r or x7r) at the output results in very low output volt- age ripple and good transient response. for lower voltages, 10f is adequate for ripple requirements but increasing c out will improve transient performance. other types and values will also work; the following discusses tradeoffs in output ripple and transient performance. the output capacitor ? lters the inductor current to generate an output with low voltage ripple. it also stores energy in order to satisfy transient loads and stabilize the lt1941s control loop. because the lt1941 operates at a high frequency, minimal output capacitance is necessary. in addition, the control loop operates well with or without the presence of output capacitor series resistance (esr). ceramic capacitors, which achieve very low output ripple and small circuit size, are therefore an option.
lt1941 12 1941fb applications information you can estimate output ripple with the following equations: v ripple = i l /(8 ? f ? c out ) for ceramic capacitors and v ripple = i l ? esr for electrolytic capacitors (tantalum and aluminum) where i l is the peak-to-peak ripple current in the inductor. the rms content of this ripple is very low so the rms current rating of the output capacitor is usually not of concern. it can be estimated with the formula: i c(rms) = i l / 12 another constraint on the output capacitor is that it must have greater energy storage than the inductor; if the stored energy in the inductor transfers to the output, the resulting voltage step should be small compared to the regulation voltage. for a 5% overshoot, this requirement indicates: c out > 10 ? l ? (i lim /v out ) 2 the low esr and small size of ceramic capacitors make them the preferred type for lt1941 applications. not all ceramic capacitors are the same, however. many of the higher value capacitors use poor dielectrics with high temperature and voltage coef? cients. in particular, y5v and z5u types lose a large fraction of their capacitance with applied voltage and at temperature extremes. because loop stability and transient response depend on the value of c out , this loss may be unacceptable. use x7r and x5r types. electrolytic capacitors are also an option. the esrs of most aluminum electrolytic capacitors are too large to deliver low output ripple. tantalum, as well as newer, lower-esr organic electrolytic capacitors intended for power supply use are suitable. chose a capacitor with a low enough esr for the required output ripple. because the volume of the capacitor determines its esr, both the size and the value will be larger than a ceramic capacitor that would give similar ripple performance. one bene? t is that the larger capacitance may give better transient response for large changes in load current. table 2 lists several capacitor vendors. table 2. low esr surface mount capacitors vendor type series taiyo-yuden ceramic avx ceramic tantalum tps kemet tantalum tantalum organic aluminum organic t491,t494,t495 t520 a700 sanyo tantalum or aluminum organic poscap panasonic aluminum organic sp cap tdk ceramic diode selection the catch diode (d1 from figure 2) conducts current only during switch off time. average forward current in normal operation can be calculated from: i d(avg) = i out (v in C v out )/v in the only reason to consider a diode with a larger current rating than necessary for nominal operation is for the worst-case condition of shorted output. the diode current will then increase to the typical peak switch current. peak reverse voltage is equal to the regulator input voltage. use a diode with a reverse voltage rating greater than the input voltage. table 3 lists several schottky diodes and their manufacturers. table 3. schottky diodes part number v r (v) i ave (a) v f at 1a (mv) v f at 2a (mv) on semiconductor mbrm120e mbrm140 20 40 1 1 530 550 595 diodes inc. b120 b130 b220 b230 20 30 20 30 1 1 2 2 500 500 500 500 international recti? er 10bq030 20bq030 30 30 1 2 420 470 470
lt1941 13 1941fb applications information boost pin considerations the capacitor and diode tied to the boost pin generate a voltage that is higher than the input voltage. in most cases, a 0.18f capacitor and fast switching diode (such as the cmdsh-3 or mmsd914lt1) will work well. figure 3 shows four ways to arrange the boost circuit. the boost pin must be more than 2.5v above the sw pin for full ef? ciency. for outputs of 3.3v and higher, the standard circuit (figure 3a) is best. for outputs between 2.8v and 3.3v, use a small schottky diode (such as the bat-54). for lower output voltages, the boost diode can be tied to the input (figure 3b). the circuit in figure 3a is more ef ? cient because the boost pin current comes from a lower voltage source. finally, as shown in figure 3c, the anode of the boost diode can be tied to another source that is at least 3v. for example, if you are generating 3.3v and 1.8v and the 3.3v is on whenever the 1.8v is on, the 1.8v boost diode can be connected to the 3.3v output. in any case, be sure that the maximum voltage at the boost pin is less than 35v and the voltage difference between the boost and sw pins is less than 25v. the boost circuit can also run directly from a dc voltage that is higher than the input voltage by more than 2.5v + v f , as in figure 3d. the diode prevents damage to the lt1941 figure 3. generating the boost voltage in case v in2 is held low while v in is present. the circuit saves several components (both boost pins can be tied to d2). however, ef? ciency may be lower and dissipation in the lt1941 may be higher. also, if v in2 is absent the lt1941 will still attempt to regulate the output, but will do so with low ef? ciency and high dissipation because the switch will not be able to saturate, dropping 1.5v to 2v in conduction. the minimum operating voltage of an lt1941 application is limited by the undervoltage lockout (3.5v) and by the maximum duty cycle. the boost circuit also limits the minimum input voltage for proper start-up. if the input voltage ramps slowly, or the lt1941 turns on when the output is already in regulation, the boost capacitor may not be fully charged. because the boost capacitor charges with the energy stored in the inductor, the circuit will rely on some minimum load current to get the boost circuit running properly. this minimum load will depend on input and output voltages, and on the arrangement of the boost circuit. the minimum load current generally goes to zero once the circuit has started. even without an output load current, in many cases the discharged output capacitor will present a load to the switcher that will allow it to start. v in boost gnd sw v in lt1941 (3a) d2 v out c3 v boost C v sw v out max v boost v in + v out v in boost gnd sw v in lt1941 (3b) d2 v out c3 v boost C v sw v in max v boost 2v in v in boost gnd sw v in lt1941 (3d) 1941 f03 v out max v boost C v sw v in2 max v boost v in2 minimum value for v in2 = v in + 3v v in2 >v in + 3v d2 v in boost gnd sw v in lt1941 (3c) v out v boost C v sw v in2 max v boost v in2 + v in minimum value for v in2 = 3v d2 v in2 > 3v c3
lt1941 14 1941fb converter with backup output regulator there is another situation to consider in systems where the output will be held high when the input to the lt1941 is absent. if the v in and one of the run/ss pins are allowed to ? oat, then the lt1941s internal circuitry will pull its quiescent current through its sw pin. this is acceptable if the system can tolerate a few ma of load in this state. with both run/ss pins grounded, the lt1941 enters shutdown mode and the sw pin current drops to ~50ma. however, if the v in pin is grounded while the output is held high, then parasitic diodes inside the lt1941 can pull large currents from the output through the sw pin and the v in pin. a schottky diode in series with the input to the lt1941, as shown in figure 4, will protect the lt1941 and the system from a shorted or reversed input. inverter/boost considerations regulating positive output voltages the output voltage is programmed with a resistor divider between the output and the fb pin. choose the resistors according to: rr v v out 34 125 1 = ? ? ? ? ? ? . ? r4 should be 10k or less to avoid bias current errors. nfb should be tied to fb3. figure 4. diode d4 prevents a shorted input from discharging a backup battery tied to the output regulating negative output voltages the lt1941 contains an inverting op-amp with its nonin- verting terminal tied to ground and its output connected to the fb3 pin. use this op-amp to generate a voltage at fb3 that is proportional to v out . choose the resistors according to: r rv v out 4 3 124 = ? . v in v in v out sw lt1941 d4 parasitic diode 1941 f04 fb3 r3 r4 1941 ai01 v out nfb fb3 r4 r3 1941 ai02 Cv out use 10k or larger, up to 20k for r3. duty cycle range the maximum duty cycle (dc) of the lt1941 inverter/boost regulator is 77%. the duty cycle for a given application using the inverting topology is: dc v vv out in out = + the duty cycle for a given application using the boost topology is: dc vv v out in out = ? the lt1941 can still be used in applications where the dc, as calculated above, is above 77%; however, the part must be operated in discontinuous mode so that the actual duty cycle is reduced. inductor selection several inductors that work well with the lt1941 inverter/ boost regulator are listed in table 4. besides these, many other inductors will work. consult each manufacturer for detailed information and for their entire selection of related parts. use ferrite core inductors to obtain the best ef? ciency. when using coupled inductors, choose one that applications information
lt1941 15 1941fb applications information can handle at least 1.5a of current without saturating and ensure that the inductor has a low dcr (copper-wire resis- tance) to minimize i 2 r power losses. if using uncoupled inductors, each inductor need only handle one-half of the total switch current so that 0.75a per inductor is suf? cient. a 4.7h to 15h coupled inductor or two 15h to 20h uncoupled inductors will usually be the best choice for most lt1941 inverter designs. a 4.7h to 15h inductor will be the best choice for most lt1941 boost designs. in this case, the single inductor must carry the entire 1.5a peak switch current. table 4. inductors part number value (h) i sat(dc) (a) dcr () height (mm) coiltronics tp3-4r7 4.7 1.5 0.181 2.2 tp4-100 10 1.5 0.146 3.0 sumida cdrh6d38np-6r2 6.2 2.5 20m 3.8 cdrh6d38np-7r4 7.4 2.3 23m 3.8 cdrh6d38np-100 10 2.0 28m 3.8 output capacitor selection use low esr (equivalent series resistance) capacitors at the output to minimize the output ripple voltage. multilayer ceramic capacitors are an excellent choice; they have an extremely low esr and are available in very small pack- ages. x7r dielectrics are preferred, followed by x5r, as these materials retain their capacitance over wide voltage and temperature ranges. a 4.7f to 20f output capacitor is suf? cient for most lt1941 applications. solid tantalum or os-con capacitors will work but they will occupy more board area and will have a higher esr than a ceramic capacitor. always use a capacitor with a suf? cient volt- age rating. diode selection a schottky diode is recommended for use with the lt1941 inverter/boost regulator. the microsemi ups120 is a very good choice. where the input to output voltage differential exceeds 20v, use the ups140 (a 40v diode). these diodes are rated to handle an average forward current of 1a. for applications where the average forward current of the diode is less than 0.5a, use an on semiconductor mbr0520l diode. the load current for boost, sepic and inverting con? gurations is equal to the average diode current. bias2 pin considerations the bias2 pin provides the drive current for the inverter/ boost switch. the voltage source on the bias2 line should be able to supply the rated current and be at a minimum of 2.5v. for highest ef? ciency, use the lowest voltage source possible (v out = 3.3v, for example) to minimize the v bias2 ? i bias2 power loss inside the part. input capacitor selection bypass the input of the lt1941 circuit with a 10f or higher ceramic capacitor of x7r or x5r type. a lower value or a less expensive y5v type will work if there is additional bypassing provided by bulk electrolytic capaci- tors, or if the input source impedance is low. the following paragraphs describe the input capacitor considerations in more detail. step-down regulators draw current from the input sup- ply in pulses with very fast rise and fall times. the input capacitor is required to reduce the resulting voltage ripple at the lt1941 input and to force this switching current into a tight local loop, minimizing emi. the input capaci- tor must have low impedance at the switching frequency to do this effectively and it must have an adequate ripple current rating. with two switchers operating at the same frequency but with different phases and duty cycles, cal- culating the input capacitor rms current is not simple; however, a conservative value is the rms input current for the channel that is delivering the most power (v out times i out ): ci vvv v i in rms out out in out in out () ? ? = () < 2
lt1941 16 1941fb applications information and is largest when v in = 2 v out (50% duty cycle). as the second, lower power channel draws input current, the input capacitors rms current actually decreases as the out-of-phase current cancels the current drawn by the higher power channel. the ripple current contribution from the third channel will be minimal. considering that the maximum load current from a single channel is ~2.8a, rms ripple current will always be less than 1.4a. the high frequency of the lt1941 reduces the energy storage requirements of the input capacitor, so that the capacitance required is often less than 10f. the combi- nation of small size and low impedance (low equivalent series resistance or esr) of ceramic capacitors makes them the preferred choice. the low esr results in very low voltage ripple. ceramic capacitors can handle larger magnitudes of ripple current than other capacitor types of the same value. use x5r and x7r types. an alternative to a high value ceramic capacitor is a lower value along with a larger electrolytic capacitor, for example a 1f ceramic capacitor in parallel with a low esr tantalum capacitor. for the electrolytic capacitor, a value larger than 10f will be required to meet the esr and ripple current requirements. because the input capacitor is likely to see high surge currents when the input source is applied, tan- talum capacitors should be surge rated. the manufacturer may also recommend operation below the rated voltage of the capacitor. be sure to place the 1f ceramic as close as possible to the v in and gnd pins on the ic for optimal noise immunity. a ? nal caution is in order regarding the use of ceramic capacitors at the input. a ceramic input capacitor can combine with stray inductance to form a resonant tank circuit. if power is applied quickly (for example by plugging the circuit into a live power source), this tank can ring, doubling the input voltage and damaging the lt1941. the solution is to either clamp the input voltage or dampen the tank circuit by adding a lossy capacitor in parallel with the ceramic capacitor. for details, see application note 88. frequency compensation the lt1941 uses current mode control to regulate the output. this simpli? es loop compensation. in particular, the lt1941 does not depend on the esr of the output capacitor for stability so you are free to use ceramic capacitors to achieve low output ripple and small circuit size. the components tied to the v c pin provide frequency compensation. generally, a capacitor and a resistor in series to ground determine loop gain. in addition, there is a lower value capacitor in parallel. this capacitor ? lters noise at the switching frequency and is not part of the loop compensation. loop compensation determines the stability and transient performance. designing the compensation network is a bit complicated and the best values depend on the application and the type of output capacitor. a practical approach is to start with one of the circuits in this data sheet that is similar to your application and tune the compensation network to optimize the performance. check stability across all operating conditions, including load current, input voltage and temperature. the lt1375 data sheet contains a more thorough discussion of loop compensation and describes how to test the stability using a transient load. application note 76 is an excellent source as well. figure 5 shows an equivalent circuit for the lt1941 control loop. the error amp is a transconductance ampli? er with ? nite output impedance. the power section, consisting of the modulator, power switch and inductor is modeled as a transconductance ampli? er generating an output cur- rent proportional to the voltage at the v c pin. note that the output capacitor integrates this current and that the capacitor on the v c pin (c c ) integrates the error ampli- ? er output current, resulting in two poles in the loop. in most cases, a zero is required and comes either from the output capacitor esr or from a resistor in series with c c . this model works well as long as the inductor current ripple is not too low (i ripple > 5% i out ) and the loop crossover frequency is less than ? sw /5. a phase lead capacitor (c pl ) across the feedback divider may improve the transient response. the equivalent circuit for the lt1941 inverter control loop is slightly different than is shown in figure 5. the feedback resistors are connected as shown for negative outputs in figure 2. the operational ampli? er is fast enough to have minimal effect on the loop dynamics.
lt1941 17 1941fb applications information table 5. converter equivalent model parameters step-down1 step-down2 boost inverter v fb 0.628v 0.628v 1.25 1.24 r o 500k 500k 500k 500k g ma 1700mho 1700mho 800mho 800mho g mp 5mho 3.6mho v in ? 5mho v out v in ? 5mho C|v out | single capacitor providing soft-start. the internal current sources will charge these pins to ~2v. the run/ss pins provide a soft-start function that limits peak input current to the circuit during start-up. this helps to avoid drawing more current than the input source can supply or glitching the input supply when the lt1941 is enabled. the run/ss pins do not provide an accurate delay to start or an accurately controlled ramp at the output voltage, both of which depend on the output ca- pacitance and the load current. however, the power good indicators can be used to sequence the three outputs, as described below. power good indicators the pgood pin is the open-collector output of an internal comparator. pgood remains low until the fb pin is within 10% of the ? nal regulation voltage. tie the pgood to any supply with a pull-up resistor that will supply less than 200a. note that this pin will be open when the lt1941 is in shutdown mode (all three run/ss pins at ground) regardless of the voltage at the fb pin. pgood is valid when the lt1941 is enabled (any run/ss pin is high) and v in is greater than ~3.5v. the 5good and 12good pins are also open-collector outputs of internal comparators. the 5good pin remains low until the input is within 10% of 5v. tie the 5good and 12good pins to any supply with a pull-up resistor that will supply less than 100a. the 12good pin remains low until the input is within 10% of 12v. the 5good and 12good pins are valid as long as v in is greater than 1.1v. both the 5good and 12good pins will sink current when the part is in shutdown, independent of the voltage at v in . output sequencing the pg and run/ss pins can be used to sequence the three outputs. figure 6 shows several circuits to do this. the techniques shown to sequence two channels can be extended to sequence the third. in each case channel 1 starts ? rst. note that these circuits sequence the outputs during start-up. when shut down the three channels turn off simultaneously. figure 5. model for loop response soft-start and shutdown the run/ss (run/soft-start) pins are used to place the individual switching regulators and the internal bias cir- cuits in shutdown mode. they also provide a soft-start function. to shut down a regulator, pull its run/ss pin to ground with an open drain or collector. if all three run/ss pins are pulled to ground, the lt1941 enters its shutdown mode with all regulators off and quiescent current reduced to ~50ma. internal 2a current sources pull up on each pin. if any run/ss pin reaches ~0.6v, the internal bias circuits start and the quiescent currents increase to their nominal levels. if a capacitor is tied from the run/ss pin to ground, then the internal pull-up current will generate a voltage ramp on this pin. this voltage clamps the v c pin, limiting the peak switch current and therefore input current during start-up. a good value for the soft-start capacitor is c out /10,000, where c out is the value of the output capacitor. the run/ss pins can be left ? oating if the shutdown feature is not used. they can also be tied together with a C + v fb v sw v c lt1941 gnd 1941 f05 r1 output esr c f c c r c 500k error amplifier fb r2 c1 c1 current mode power stage g mp g ma + polymer or tantalum ceramic c pl
lt1941 18 1941fb applications information in figure 6a, a larger capacitor on run/ss2 delays channel 2 with respect to channel 1. the soft-start capacitor on run/ss2 should be at least twice the value of the capacitor on run/ss1. a larger ratio may be required, depending on the output capacitance and load on each channel. make sure to test the circuit in the system before deciding on ? nal values for these capacitors. the circuit in figure 6b requires the fewest components, with both channels sharing a single soft-start capacitor. the power good comparator of channel 1 disables chan- nel 2 until output 1 is in regulation. for independent control of channel 2, use the circuit in figure 6c. the capacitor on run/ss1 is smaller than the capacitor on run/ss2. this allows the lt1941 to start up and enable its power good comparator before run/ss2 gets high enough to allow channel 2 to start switching. channel 2 only operates when it is enabled with the external control signals and output 1 is in regulation. the circuit in figure 6a leaves both power good indica- tors free. however, the circuits in figures 6b and 6c have another advantage. as well as sequencing the two outputs at start-up, they also disable channel 2 if output 1 falls out of regulation (due to a short circuit or a collapsing input voltage). figure 6. several methods of sequencing two ouputs. channel 1 starts first off 1941 f06 run/ss1 pg1 on gnd off run/ss1 lt1941 lt1941 on gnd run/ss2 off run/ss1 on off2 on2 gnd run/ss2 run/ss2 v c2 pg1 1nf 1nf 1nf 2.2nf 1nf 1.5nf 1.5nf (6b) fewest components (6c) independent control of channel 2 off run/ss1 on gnd run/ss2 pg1 (6d) doesn't work ! (6a) channel 2 is delayed lt1941 lt1941 finally, be aware that the circuit in figure 6d does not work , because the power good comparators are disabled in shutdown. pcb layout for proper operation and minimum emi, care must be taken during printed circuit board (pcb) layout. figure 7 shows the high current paths in the step-down regulator circuit. note that in the step-down regulators large, switched currents ? ow in the power switch, the catch diode and the input capacitor. in the inverter/boost regulator large, switched currents ? ow through the power switch, the switching diode, and either the output capacitor in boost con? guration, or the tank capacitor in the inverter con- ? guration. the loop formed by these components should be as small as possible. place these components, along with the inductor and output capacitor, on the same side of the circuit board and connect them on that layer. place a local, unbroken ground plane below these components and tie this ground plane to system ground at one loca- tion, ideally at the ground terminal of the output capacitor c2. additionally, keep the sw and boost nodes as small as possible.
lt1941 19 1941fb applications information thermal considerations the pcb must provide heat sinking to keep the lt1941 cool. the exposed pad on the bottom of the package must be soldered to a ground plane. this ground should be tied to other copper layers below with thermal vias; these lay- ers will spread the heat dissipated by the lt1941. place additional vias near the catch diodes. adding more copper to the top and bottom layers and tying this copper to the internal planes with vias can reduce thermal resistance further. with these steps, the thermal resistance from die (or junction) to ambient can be reduced to ja = 25c/w or less. with 100 lfpm air? ow, this resistance can fall by another 25%. further increases in air? ow will lead to lower thermal resistance. because of the large output current capability of the lt1941, it is possible to dissipate enough heat to raise the junction temperature beyond the absolute maximum of 125c. if two of the channels are running at full output current, the third channel may have reduced output current capability, limited by the maximum junction temperature. the output figure 7. subtracting the current when the switch is on (a) from the current when the switch is off (b) reveals the path of the high frequency switching current (c) keep this loop small. the voltage on the sw and boost nodes will also be switched; keep these nodes as small as possible. finally, make sure the circuit is shielded with a local ground plane figure 8. power path components and topside layout v in sw gnd (a) v in v sw c1 d1 c2 1941 f07 l1 sw gnd (c) v in sw gnd (b) i c1 gnd gnd gnd v out1 v in c in1 c in2 l3 l4 l1 1941 f08 c7 c12 c10 c11 d1 c8 d3 place vias under ground pad to ground plane for good thermal conductivity d4 d5 d2 u1 v out2 v out3 gnd c9
lt1941 20 1941fb applications information current capability of the third channel can be calculated from the output currents and voltages of the other chan- nels, the switching regulator ef? ciency ( ), the ambient temperature (t a ), the maximum junction temperature (t jmax ) and the thermal resistance from junction to ambi- ent ( ja ) as follows: p tt p p vi v i i diss jmax a ja diss = = = ? ? ??? ? 3 1 12 12 3 p p v 3 3 example: lt1941 at v1 = 2.5v, i 1 = 2a, v2 = 3.3v, i 2 = 1a, v3 = 12v, = 80%, t a = 75c, t jmax = 125c, ja = 25c/w: p cc cw w p w va diss = = = 125 75 25 2 3 2 108 25 2 ? / ?. ?. ? ? ?. ? . . . 33 1 17 17 12 0 141 3 va w i w v a = == note that decreasing ja increases the power output capability. the power output capability of the individual channels can be calculated from the following: channel 1 output power (p1) = v1 ? i 1 channel 2 output power (p2) = v2 ? i 2 channel 3 output power (p3) = v3 ? i 3 total output power (p123) = p diss / = p1 + p2 + p3 figure 9 shows power output capability if overall system ef? ciency ( ) is 75% and maximum allowable power dissipation (p diss ) is either 1w or 2w. for example, if al- lowable power dissipation is 2w, channel 3 output power is 2w and channel 2 output power is 1w, then channel 1 output power can be up to 5w. related linear technology publications application notes 19, 35, 44, 76 and 88 contain more detailed descriptions and design information for buck regulators and other switching regulators. the lt1375 data sheet has a more extensive discussion of output ripple, loop compensation, and stability testing. design notes 100 and 318 show how to generate a dual polarity output supply using a buck regulator. figure 9. power output capability of an individual channel depends on the output power of the other channels power output capability for p diss = 2w, = 0.75 power output capability for p diss = 1w, = 0.75 channel 1 output power (watts) 0 0 channel 2 output power (watts) 1 2 3 4 6 1 234 1941 f09a 56 5 channel 3 output power (p3) p3 = 2w p3 = 4w p3 = 6w channel 1 output power (watts) 0 0 channel 2 output power (watts) 0.5 1.0 1.5 2.0 3.0 12 1941 f09b 3 2.5 channel 3 output power (p3) p3 = 1w p3 = 2w p3 = 3w
lt1941 21 1941fb applications information slic power supply C21.6v, C65v, 3.3v and 1.8v with soft-start v in lt1941 gnd pgnd c2 0.22f c4 22f c13 1000pf c15 1.5nf c14 1.5nf c12 3300pf r5 10.2k r15 1 r13 178k r11 2.49k r10 10k v in 5v 5good 12good v out1 1.8v 2.4a v out3 C21.6v 72ma v out4 C65v 30ma l2 3.3h l1 3h l3 2.7h r12 10.7k r7 13.7k r6 7.32k r4 3.3k r14 15k 1941 ta01 r2 130k r1 100k r3 100k r8 100k r9 100k d2 d4 pgood1 pgood2 pgood3 v out2 3.3v 1.4a c1 0.22f d1 c3 33f d3 c5 1f 35v c6 10f c7 4.7f 25v c8 1f 35v c10 1f 35v c16 4700pf pgood1 pgood2 pgood3 boost2 fb2 v c2 fb1 v c1 runss2 bias1 bias2 v c3 runss3 runss1 sw3 nfb fb3 5good 12good boost1 c17 1.5nf note: total output power of v out3 and v out4 not to exceed 1.9w c1 to c11: x5r or x7r d1, d2: cmdsh-3 d3: b220a d4: mbrm120l d5 to d7: bav99 or equivalent sw2 sw1 d5 v out2 v out1 c9 4.7f 25v d6 c11 4.7f 25v d7
lt1941 22 1941fb typical applications quadruple output power supply: 12v, 3.3v and 2.5v with soft-start v in v out3 v out2 v out1 lt1941 gnd pgnd c2 0.22f c4 22f c12 1000pf c13 1.5nf c11 1.5nf c10 1000pf r5 13.7k r13 118k r11 2.49k r10 10k v in 5v 5good 12good v out1 2.5v 2.3a v out3 12v 100ma v out4 C12v 100ma l2 3.3h l1 3h l3 10h r12 10.7k r7 10.2k r6 3.4k r4 10k r14 2.2k c1 to c9: x5r or x7r d1, d2: cmdsh-3 d3: b220a d4: mbrm120l d5 to d8: mbr0540 1941 ta02 r2 130k r1 100k r3 100k r8 100k r9 100k d2 d4 pgood1 pgood2 pgood3 v out2 3.3v 1.4a c1 0.22f d1 c3 33f 1 c5 4.7f c9 4.7f d5 d8 d3 d7 d6 c6 10f c7 10f c8 10f c14 6800pf pgood1 pgood2 pgood3 boost2 fb2 v c2 fb1 v c1 runss2 bias1 bias2 v c3 runss3 runss1 sw3 nfb fb3 5good 12good boost1 c15 1.5nf sw2 sw1 triple output power supply: 3.3v, 1.8v and C12v v out2 v out1 lt1941 v in gnd c2 0.22f c4 22f c10 1000pf c11 1.5nf c9 1.5nf c8 3300pf 13.7k 133k 2.49k 10k v in 4.7v to 14v 5good 12good v out1 1.8v 2.4a v out3 C12v 350ma* 3.3h 3h 22h 22h 10.7k 13.7k 7.32k 3.3k 1.5k c1-c7: x5r or x7r d1, d2: cmdsh-3 d3: b220a d4: ups120 d5: b130 1941 f01 130k 100k 100k 100k 100k pgood1 pgood2 pgood3 v out2 3.3v 1.4a c1 0.22f c3 33f c5 1f c7 10f *240ma at v in = 5v, 550ma at v in = 12v c6 10f c12 22nf pgood1 pgood2 pgood3 boost2 sw2 fb2 v c2 sw1 fb1 v c1 runss2 bias1 bias2 v c3 runss3 runss1 sw3 nfb fb3 5good 12good boost1 c13 1.5nf
lt1941 23 1941fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. fe28 (eb) tssop 0204 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 134 5 6 7 8910 11 12 13 14 19 20 22 21 15 16 18 17 9.60 ? 9.80* (.378 ? .386) 4.75 (.187) 2.74 (.108) 28 2726 25 24 23 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 0.195 ? 0.30 (.0077 ? .0118) typ 2 recommended solder pad layout exposed pad heat sink on bottom of package 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 4.75 (.187) 2.74 (.108) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc package description fe package 28-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663) exposed pad variation eb
lt1941 24 1941fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2004 lt 0409 rev b ? printed in usa related parts part number description comments lt1613 550ma (i sw ), 1.4mhz, high ef? ciency step-up dc/dc converter v in : 0.9v to 10v, v out(max) = 34v, i q = 3ma, i sd < 1a, thinsot? package lt1615/lt1615-1 300ma/80ma (i sw ), high ef? ciency step-up dc/dc converter v in : 1v to 15v, v out(max) = 34v, i q = 20a, i sd < 1a, thinsot package lt1617/lt1617-1 300ma/100ma (i sw ), 1.2mhz/2.2mhz, high ef? ciency inverting dc/dc converter v in : 1.2v to 15v, v out(max) = C34v, i q = 20a, i sd < 1a, thinsot package lt1618 1.5a (i sw ), 1.25mhz, high ef? ciency step-up dc/dc converter v in : 1.6v to 18v, v out(max) = 35v, i q = 1.8ma, i sd < 1a, ms10 package lt1930/lt1930a 1a (i sw ), 1.2mhz/2.2mhz, high ef? ciency step-up dc/dc converter v in : 2.6v to 16v, v out(max) = 34v, i q = 4.2ma/5.5ma, i sd < 1a, thinsot package lt1931/lt1931a 1a (i sw ), 1.2mhz/2.2mhz, high ef? ciency inverting dc/dc converter v in : 2.6v to 16v, v out(max) = C34v, i q = 5.8ma, i sd < 1a, thinsot package lt1943 quad output, 2.6a buck, 2.6a boost, 0.3a boost, 0.4a inverter 1.2mhz tft dc/dc converter v in : 4.5v to 22v, v out(max) = 40v, i q = 10ma, i sd < 35a, tssop28e package lt1944-1 dual output 150ma (i sw ), constant off-time, high ef? ciency step-up dc/dc converter v in : 1.2v to 15v, v out(max) = 34v, i q = 20a, i sd < 1a, ms10 package lt1944 dual output 350ma (i sw ), constant off-time, high ef? ciency step-up dc/dc converter v in : 1.2v to 15v, v out(max) = 34v, i q = 20a, i sd < 1a, ms10 package lt1945 dual output pos/neg 350ma (i sw ), constant off-time, high ef? ciency step-up dc/dc converter v in : 1.2v to 15v, v out(max) = 34v, i q = 20a, i sd < 1a, ms10 package lt1946/lt1946a 1.5a (i sw ), 1.2mhz/2.7mhz, high ef? ciency step-up dc/dc converter v in : 2.45v to 16v, v out(max) = 34v, i q = 3.2ma, i sd < 1a, ms8 package lt1961 1.5a (i sw ), 1.25mhz, high ef? ciency step-up dc/dc converter v in : 3v to 25v, v out(max) = 35v, i q = 0.9ma, i sd < 6a, ms8e package lt3436 3a (i sw ), 1mhz, 34v step-up dc/dc converter v in : 3v to 25v, v out(max) = 34v, i q = 0.9ma, i sd < 6a, tssop16e package lt3461/lt3461a 300ma (i sw ), high ef? ciency step-up dc/dc converter with integrated schottky and soft-start v in : 2.5v to 16v, v out(max) = 38v, i q = 2.8ma, i sd < 1a, thinsot package lt3463 dual output pos/neg 250ma (i sw ), constant off-time, high ef? ciency step-up dc/dc converter with integrated schottkys v in : 2.4v to 15v, v out(max) = 40v, i q = 40a, i sd < 1a, 3mm 3mm dfn10 package lt3464 85ma (i sw ), high ef? ciency step-up dc/dc converter with integrated schottky and pnp disconnect v in : 2.3v to 10v, v out(max) = 34v, i q = 25a, i sd < 1a, thinsot package thinsot is a trademark of linear technology corporation.

▲Up To Search▲

Price & Availability of LT1941-15

	To Download LT1941-15 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .